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Tunneling MOSFETs Based on III-V Staggered Heterojunctions

Published online by Cambridge University Press:  01 February 2011

Peter Asbeck
Affiliation:
asbeck@ece.ucsd.edu, UCSD, ECE, La Jolla, California, United States
Lingquan Wang
Affiliation:
liw001@ucsd.edu, UCSD, ECE, La Jolla, California, United States
Siyuan Gu
Affiliation:
gusiyuan@gmail.com, UCSD, ECE, La Jolla, California, United States
Yuan Taur
Affiliation:
taur@ece.ucsd.edu, UCSD, ECE, La Jolla, California, United States
Edward Yu
Affiliation:
ety@ece.utexas.edu, UT Austin, ECE, Austin, Texas, United States
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Abstract

A critical problem for the progression of CMOS electronics to the nanoscale is the reduction of power density, while at the same time preserving high speed performance. One of the most promising approaches is to aggressively reduce the power supply voltage by using a novel device, the tunneling MOSFET (TMOSFET), which is a MOSFET that operates by tunnel-injection of carriers from source to channel, rather than by conventional thermionic emission. TMOSFETs benefit from steep (sub-60mV/dec) gate turn-on characteristics. In this paper we show that TMOSFET designs based on staggered heterojunctions are particularly promising, since the choice of materials for the injector (source) and channel allows optimization of the tunneling probability at the heterojunction. Analysis and simulation of MOSFETs based on the GaAlSb / InGaAs material system are presented. The energy offset between the valence band of the injector and the conduction band of the channel at the heterojunction can be tailored over a wide range, from negative values (“offset” band lineup) to values in excess of 1eV. We find by simulation that for optimal values of effective heterojunction bandgap near 0.2eV, the resulting MOSFETs are capable of delivering >0.5mA/mm while maintaining on-off ratio greater than four orders of magnitude over voltage swing of 0.3V. We also discuss a variety of materials-related challenges that must be overcome to realize the predicted performance. Among these are the need to provide near ideal heterojunctions between the materials, employ high K dielectrics with very low interface state density, and achieve good alignment between the gate and the heterojunction. Different configurations for the tunneling MOSFETs are presented.

Type
Research Article
Copyright
Copyright © Materials Research Society 2010

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