The outstanding performance of the SiGe/Si heterosystem and its compatibility to the dominating Si-technology, opens perspectives for a new generation of high volume microelectronic components, just for communication markets. This paper reviews device and circuit results from experiments and simulations for SiGe HBTs and for SiGe HFETs, and compares those to device results made from competitive materials. Figures of merit considered are gains, transconductances, frequencies, noise, power, delays and bandwidths.

The SiGe HBT, integrated with CMOS devices on the same chip, will be the first integrated device combination to realize the long-standing technology goal of fabricating RF systems on a chip. It has been demonstrated that the HBT device can replace the standard GaAs front-end of RF systems and take advantage of the reduced cost available from Si technologies in 200–300mm wafers. However, the SiGe HBT can only be part of a large-scale RF system on a chip when, in the same technology, NFETs and PFETs are provided for low power, low frequency digital logic, and a suite of resistors, capacitors, diodes, and inductor passive elements are provided for the high frequency analog circuitry. Furthermore, all these elements must be manufacturable defect-free at medium and high levels of integration.

This paper covers keyprocess integration issues confronting technologists when integrating a SiGe HBT device with the requisite CMOS and passive elements and at the same time maintaining very high GaAs-like performance. Topics to be discussed are 1) a review of high-performance HBT device integration schemes employed to date and integration issues with each scheme, 2)integration issues in epitaxial cleaning and growth techniques, 3) integration issues influencing crystal defects, and 4) integration issues with passive elements. Status of the IBM SiGe BiCMOS technology will be presented to illustrate the first successful integration of this set of devices into a manufacturable process.

We examine the velocity overshoot effect in strained Six on Six-Ge1-x heterostructures. We also investigate the performance of surface-channel strained-Si MOSFETs for devices with gate lengths representative of the state-of-the-art technology. The Ensemble Monte Carlo method, self-consistently coupled with the 2D Poisson equation solver, is used in the investigation of the device performance. Our simulations suggest that, in short-channel devices, velocity overshoot is very important. In fact, when velocity overshoot occurs, it greatly affects the carrier dynamics and the current enhancement factor of both surface-channel strained-Si and conventional Si MOSFETs.

The first demonstration of n-MOSFETs fabricated using strained Si1-yCy surface channels is reported. Tensile-strained Si1-yCy layers with substitutional carbon contents up to 0.8 atomic percent were epitaxially grown on <100> Si substrates by rapid thermal chemical vapor deposition, using silane and methylsilane as the silicon and carbon precursors. n-MOSFETS were fabricated using standard MOS processing with reduced thermal exposure to minimize the possibility of strain relaxation. A remote plasma CVD oxide was employed to form the gate oxide. The Si1-yCy devices exhibit electrical characteristics that are typical for Si n-MOSFETs, with good turn-on and subthreshold characteristics. MOS capacitance-voltage analysis demonstrates comparable oxide interface qualities for the Si1-yCy and Si control devices. No carbon-related leakage current is observed in source and drain diode junctions. Characterization of the MOSFET electron inversion layer mobility at room temperature shows comparable mobilities, within the sensitivity of the measurement, for the Si1-yCy and Si control devices. This is in contrast to the mobility enhancement observed in n-MOSFETs fabricated using tensile- strained Si grown on relaxed Si1-xGex layers. At low temperatures, the inversion layer mobility of Si1-yCy devices is lower than that of the Si controls, and appears to be affected by Coulomb and possibly random alloy scattering.

In this work, we have investigated the reaction between Zr and SiGeC alloys after Rapid Thermal anneals performed at 800°C for 5 min. The interactions of the metal with the alloy have been investigated by X-Ray diffraction. Four crystal X-Ray diffraction was also performed to measure the residual strain in the epilayer. The final compound of the reaction is the C49- Zr(Si1-xGex)2 phase. The C49 film contains the same Ge concentration as in the as-deposited Si1-x-yGexCy layer. This suggests that no Ge-segregation occurs during annealing. Only a small strain relaxation is detected in the unreacted SiGe epilayer during the reaction. The addition of C in the epilayer prevents any strain relaxation. These results are in contrast with those observed in systems with Ti and Co, and show that the system Zr-Si-Ge is much more stable. Schottky barrier heights have been also measured: annealing leads to a slight decrease of the barrier without any degradation of the contact. The resistivity of the C49 film is about 80 μΩcm. These results indicate that Zr may be a good candidate for contacts on IV-IV alloys in term of thermal stability.

Si/Si1-xGex, heterostructures on improved silicon-on-sapphire substrates were grown epitaxially by ultra-high vacuum chemical vapor deposition for application as p-channel field effect transistors. High-resolution triple-axis x-ray diffraction was used to analyze these structures quantitatively and to evaluate the effects of device fabrication processes on them. Out-;diffusion of Ge from the Si1-xGex, quantum well was observed after fabrication as was the change in thickness of the Si cap layer due to wafer cleaning and gate oxidation at 875 °C

Raman scattering studies were carried out on epi Si/Si1-xGex (x = 0.1 to 0.3) heterostructures consisting of a thin Si cap layer (100 - 400 A˚), a grade-down Si1-xGex layer, a constant Si1-xGex, buffer layer and a grade-up graded Si1-xGex layer on (100) oriented Si substrates. Different Ge composition, Si1-xGex layer thicknesses and thermal treatment were used to achieve different relaxation in the Si1-xGex layers. It has been revealed that, to a very good approximation, the absolute strains in the cap Si and constant Si1-xGex layers follow a simple sum-rule that is imposed by the lattice mismatch between unstrained Si and completely relaxed Si1-x Gex. This sum rule can be used to determine the Ge composition and stresses in both cap Si and constant Si1-xGex layers. Excellent agreement was found between the theoretical curve obtained with LO phonon strain coefficient b=−930cm−1 and the experimental total strain for all samples, regardless of the degree of the relaxation of the grade-up Si1-xGex layer.

Si1-xGex/Si heterostructures with different layer thicknesses grown by selective LPCVD epitaxy at different growth temperatures were investigated with regard to plastic relaxation. AFM and optical micrograph were performed to determine the dislocation density. From the analysis of the misfit dislocations at the initial stage of relaxation of the samples grown at 700°C it was possible to determine the nucleation site density and an activation energy of 2.8 eV for the heterogeneous nucleation of misfit dislocations. While the critical thickness hc for a given Ge content increases with decreasing growth temperature between 800°C-680°C one observes a dramatic decay of hc, at a growth temperature of 625°C. For growth at 625°C it was found that this activation barrier is drastically decreased.

In recent years the growth of virtual substrates using graded SiGe buffer layers has shown great promise for the development of high performance devices. Whilst significant progress has been made in the control of growth conditions to produce low threading dislocation densities of the order suitable for commercial exploitation, several technological problems still have to be overcome. An example of such problems are cosmetic surface defects such as pits and the cross hatched surface roughness associated with mosaic crystal tilts. The work described here utilises a variety of techniques, including X-ray diffraction reciprocal space maps, TEM, AFM and SIMS to provide a comparison between several SiGe virtual substrates grown using low pressure-CVD at high (≈800°C) and low (≈6000°C) temperatures, and at different grade rates (5–50% Ge μm−1). The growth conditions are seen to have a strong effect on the crystal tilts present in the layers with the low temperature layers showing a much larger spread of mosaic tilts. The origin of these tilts is seen to occur during the early stages of the relaxation process irrespective of growth temperature and at similar Ge fractions for all samples. TEM imaging close to the initial growth interface shows that dislocation pileups occur in this region and also suggest that the pileups have a characteristic spacing of 1–2μm. A similar characteristic length scale is also observed in the surface roughness by AFM, the form of which is seen to depend upon the growth conditions.

A review of the latest results on high performance Si/SiGe FETs grown on relaxed buffer is presented. A discussion of the fabrication issues facing the achievement of these devices is also included.

Poly-SiGe stacked gates with Ge content ([Ge])varying between zero and 100% have been fabricated using an industriel single-wafer machine. These poly-SiGe layers were characterised and fully integrated in a 0.18 pm CMOS process. Interdiffusion of Si and Ge upon subsequent annealing of the structure has been observed and studied. This interdiffusion effect was found to be responsible for the discrepancy observed between theoretical and practical values of the Ge workfunction ɸms evaluated from our electrical measurements and from those of different authors. A technique for the limitation of this interdiffusion effect has then been developped and is described.

The degradation of the electrical performance of strained Si1-xGex epitaxial diodes by 220-MeV carbon particles is reported and compared with the effect of 20-MeV alpha rays and 20-MeV protons. The macroscopic damage is studied in a broad fluence range and for different Ge contents, ranging from 8 to 16 %. It is shown that the radiation damage of carbon irradiated diodes is about one order of magnitude larger than that for alpha ray irradiation, which can be explained by considering the difference of the nonionizing energy loss (NIEL). It is observed that the reverse current at a fixed bias increases with increasing fluence, while the rate of increase decreases with increasing fluence and/or Ge content. The fact that a close to square root dependence exists between the boron deactivation in the diode depletion region, derived from capacitance-voltage measurements and the reverse current increase suggests that the device degradation is dominated by radiation induced deep levels associated with interstitial boron complexes.

The boron out-diffusion into the Si collector of SiGe HBT's with implanted emitters is compensated by an epitaxially grown n+ phosphorus peak effectively positioned adjacent to the as-grown boron peak. Detrimental barrier formation is suppressed in devices with base sheet resistance 3.3 k.Ω and cut-off frequency of 31 GHz.

Wet and dry oxidations of polycrystalline SixGe1-x, with various compositions have been studied at different temperatures. The growth rate of SiO2 is found to be enhanced by Ge, and the enhancement effect is more pronounced in H2O than in O2. A mathematical model, which assumes simultaneous oxidation of Si and Ge and reduction of GeO2 by free Si available at the growing-oxide/SixGe1-x interface, is found to give a quantitative description of the SiO2 growth during thermal oxidation of SixGe1-x. Kinetic parameters are extracted by comparing the model with experiments. The linear and parabolic rate constants for Si oxidation are determined on control Si (100) wafers and polycrystalline Si films. Simple expressions are used for the interdiffusion of Si and Ge in SixGe1-x. For wet oxidation, the activation energy for the reaction rate constant of Ge oxidation is found to be smaller than that of Si oxidation.

Material and electrical characterization of n-type and p-type Si1-x-yGex Cy epitaxial layers on Si(100) was performed using silicided platinum Schottky contacts. XRD studies show Pt silcidation of SiGeC proceeds from non-reacted Pt to Pt2(SiGeC) and completes with the Pt(SiGeC) phase similar to Pt/Si silicides, but Pt silicide reactions with SiGeC are shown to require higher temperatures than Pt reactions with Si. Electrical characterization of Pt(SiGeC) contacts to n-type Sil1-x-yGexCx/Si shows rectifying behavior with constant barrier heights of 0.67eV independent of composition, indicating Fermi level pinning relative to the SiGeC conduction band is occurring. Pt(SiGeC) contacts to p-type Si1-x-yGexCy/Si are also rectifying with barrier heights that track the variation of the SiGeC energy bandgap.

We measured the pseudodielectric function (PDF) of Ge1-yCy and Ge-rich Si1-x-yGexCy alloys from 1.1 to 5.2 eV using spectroscopic ellipsometry. These alloys were grown by molecular beam epitaxy at 6000C on (001) Si substrates. Analytical lineshapes fitted to numerically calculated derivatives of their PDFs determined the critical-point parameters of the E1, E1+Δ1, E0', and E2 transitions. The critical-point energies of the Ge1-yCy alloys were found to be similar to bulk Ge. This indicates that the presence of C in these alloys only has a small influence on the band structure. For some samples, the amplitude of the PDF is much lower than in bulk Ge, which can be attributed to surface roughness and explained within the framework of the Kirchhoff theory of diffraction or using effective medium theory. The degree of surface roughness indicated by optical measurements was confirmed by atomic force microscopy. We also studied bulk Czochralski-grown Si1-xGex alloys (0<x<0.28) doped with boron. Due to doping, the critical points shift to lower energies as reported previously for bulk Si and Ge.

UHVCVD-grown SiO.s 7Ge0.13/Si heterostructures have been implanted with erbium, and photoluminescence and electroluminescence centred on 1.54ýim have been studied. Implantation conditions were chosen so that the erbium concentration profile was flat over the spatial location of the SiGe quantum well region. We demonstrate that the technology of implantation and regrowth is feasible even when Si/SiGe interfaces are present. We have obtained more intense photoluminescence from erbium implanted SiGe heterostructures than that from a silicon layer implanted with a higher erbium dose. We report forward bias electroluminescence from the Er doped SiGe/Si heterostructures; the photoluminescence and electroluminescence from these structures demonstrates that the detailed mechanism of excitation is different from the Er:Si case.

We have fabricated erbium- and oxygen-doped Si/SiGe waveguide diodes showing the characteristic 1.54 µm electroluminescence (EL) from incorporated Er+3, ions. All samples were grown by molecular beam epitaxy (MBE). The EL from the polished end facet of the waveguide was measured with a confocal microscope revealing a spatially narrow emission. Additional annealing was not necessary to improve the luminescence characteristics. Only a weak temperature dependence is found for the EL intensity between 4K and room temperature.

Polycrystalline silicon-germanium (poly-Si1-xGex) thin film transistors (TFTs) werefabricated with and without Si interlayers (caps) to buffer the SiO2 gate dielectric and theSi1-xGex channel. Both low temperature processes (≤ 550 °C) compatible with glass for flat panel displays and high temperature processes were used. NMOS TFTs show dramatic performanceimprovements up to moderate (5 to 10 nm) interlayer thicknesses. In contrast, PMOS TFTs showonly small improvements at low interlayer thicknesses (< 5 nm), after which performancedeclines. Computer simulations using an effective medium model for polycrystalline materialssuggest that in addition to interface improvement, a pseudomorphic heterojunction is formedfrom the strained Si cap and unstrained poly-Si1-xGex channel with both conduction and valenceband offsets. These offsets play a significant role in inversion layer formation.

The formation of macropore arrays with high aspect ratios by electrochemical etching of n-type silicon in hydrofluoric acid is a well established technique. By using standard photolithograpy the geometry of the array can be controlled with high precision. This enables us to fabricate twodimensional photonic crystals for the infrared regime. The calculated photonic band structure of the crystal corresponds well with the transmission observed experimentally. Furthermore first defect structures like waveguides and cavities have been realized.