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Wafer Level Modeling of Electrochemical-Mechanical Polishing (ECMP)

Published online by Cambridge University Press:  01 February 2011

Daniel Truque ,
Xiaolin Xie  and
Duane Boning
Daniel Truque
Affiliation:
truque@mit.edu, Massachusetts Institute of Technology, Electrical Engineering and Computer Science, 70 Pacific St Apt. 902A, Cambridge, MA, 02139, United States, 7862521268
Xiaolin Xie
Affiliation:
xiaolin@alum.mit.edu, Massachusetts Institute of Technology, Microsystems Technology Laboratories, Cambridge, MA, 02139, United States
Duane Boning
Affiliation:
boning@mtl.mit.edu, Massachusetts Institute of Technology, Microsystems Technology Laboratories, Cambridge, MA, 02139, United States
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Abstract

In this work, we propose a wafer level dynamic ECMP model based on time-evolving current density distributions across the wafer. The copper layer on the wafer surface is discretized, and the potential and current density distributions are calculated based on the applied voltage zones and metal film thicknesses across the wafer. The copper removal rate is proportional to the current density, and thus the copper thickness (and conductance) can be calculated as a function of position on the wafer and polish time. Using a time-stepping simulation, the model is able to capture the wafer level non-uniformity and time-dependence of ECMP removal. The model is also able to capture the time-varying voltage zones used in ECMP, and can be used to find optimal voltage zone control schemes to achieve improved wafer-level uniformity.

Keywords

CMPCuelectrochemical synthesis
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 991: Symposium C – Advances and Challenges in Chemical Mechanical Planarization , 2007 , 0991-C11-04
Copyright
Copyright © Materials Research Society 2007

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References

REFERENCES

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