Dysprosium oxide (Dy2O3) films are grown epitaxially on high mobility Ge(100) substrates by molecular beam epitaxy system. Reflection high energy electron diffraction patterns and X-ray diffraction spectra show that single crystalline cubic Dy2O3 films are formed on Ge(100) substrates. The epitaxial-relationship is identified as Dy2O3 (110)║Ge(100) and Dy2O3 [001]║Ge[011]. Atomic force microscopy results show that the surface of the Dy2O3 film is uniform, flat and smooth with root mean square surface roughness of about 4.6Å. X-ray photoelectron spectroscopy including depth profiles confirms the composition of the films being close to Dy2O3. TEM measurements reveal a sharp, crystalline interface between the oxide and Ge.

The optical properties of an InAsP/InP quantum well grown on a SrTiO3(001) substrate are analyzed. At 13K, the photoluminescence (PL) yield of the well is comparable to that of a reference well grown on an InP substrate. Increasing the temperature leads to the activation of non-radiative mechanisms for the sample grown on SrTiO3. The main non-radiative channel is related to the thermal excitation of the holes to the first heavy hole excited state, followed by the non-radiative recombination of the carriers on twins and/or domain boundaries, in the immediate vicinity of the well.

In this work, the effect of elevated temperature on the generated defects with constant voltage stress (CVS) in SiO2 and SiO2/HfSiO stacks is investigated. Applying Trap Spectroscopy by Charge Injection and Sensing (TSCIS) to 6.5 nm SiO2 layers, different kinds of generated traps are profiled at low and high temperature. Also the Stress-Induced Leakage Current (SILC) spectrum of high-k dielectric stack is different at elevated temperature indicating that degradation and breakdown at high temperature is not equivalent to that at low temperature and therefore, extrapolation of data from high to low T or vice versa is challenging.

The impact of interfacial oxygen content on the band offsets of GaAs:HfO2 interfaces was investigated using the density functional theory (DFT) method. Reference potential method was used to determine the band offsets. Moreover, GW correction was utilized to find more accurate value of the valence band edge of HfO2 and hence obtain more accurate band offsets. With gradually decreasing the interfacial O content from 100% to 30% (by changing O chemical potential corresponding to varying the growth condition), the valence band offset increases from 1.06 to 3.34 eV. It is found that this increase of the valence band offsets is inversely proportional to the charge loss of interfacial Ga atoms. Specifically, less charge loss of interfacial Ga induces less charge transfer from GaAs to HfO2 side. Consequently, the less charge loss of interfacial Ga essentially leads to an increase of the valence band offsets.

We have investigated the integration of Hf-based material as Inter Poly Dielectric in flash memories devices. Electrical measurements showed the good properties of SiO2/HfO2/SiO2 stacks. We then interested to the impact of the thermal budget on this specific stack which induces changes in the electrical properties. XPS measurements suggests those changes are due to the presence of an Hf-silicate layer at the SiO2/HfO2 interface.

The multiple-gate aspect of the Screen Grid Field Effect Transistor (SGrFET) increases functionality and reduces component count of circuits. An independently-driven gate SGrFET is used to control the switching voltage as well as the gain factor of an inverter. The multi-gate configuration of the SGrFET allows a decrease in output conductance without an increase of transistors count. This leads to a reduction in fabrication complexity, chip area and parasitics. In addition, a simple SGrFETs-based current mirror circuit is proposed with gain factor control.

This work reports on the epitaxial growth of crystalline high-k Gd2O3 on Si (111) by Molecular Beam Epitaxy (MBE) for CMOS gate application. Epitaxial Gd2O3 films of different thicknesses have been deposited on Si (111) between 650°C~750°C. Electrical characterizations reveal that the sample grown at the optimal temperature (700°C) presents an equivalent oxide thickness (EOT) of 0.73nm with a leakage current density of 3.6×10-2 A/cm2 at |Vg-VFB|=1V. Different Post deposition Annealing (PDA) treatments have been performed for the samples grown under optimal condition. The Gd2O3 films exhibit good stability and the PDA process can effectively reduce the defect density in the oxide layer, which results in higher performances of the Gd2O3/Si (111) capacitor.

LPCVD Ge films are deposited onto bulk Si substrates and subjected to either a rapid thermal anneal (RTA) or furnace anneal (FA) at a temperature that is higher than the melting point of Ge in an attempt to induce epitaxial recrystallization. Spiking into the Si and voids in the Ge film are observed after the anneal. This is attributed to defect-assisted Ge diffusion into the Si substrate caused by strain at the Ge-Si interface. Simple diffusion theory using published diffusivity values predicts diffusion depths similar to the spiking depths observed by scanning electron microscopy and transmission electron microscopy. Approaches to reduce the strain at the interface are explored. It is found that the quasi-equilibrium nature of FA reduces spiking and that there is an area dependence. Grazing-incidence x-ray diffraction analysis suggests that this technique for epitaxial recrystallization does not result in single-crystalline Ge.

A new type of silicon-based Vertical MOSFET concept is presented - Single-Device CMOS (SD-CMOS) - in which the same structure can be operated as NFET or as PFET, depending on the biasing conditions [1]. SD-CMOS offers new possibilities for CMOS integration schemes that are simpler - requiring only 5 masks for the “Front- End” - and less costly to manufacture, than any integration scheme requiring the fabrication of two devices with opposite polarities.

In epitaxially grown Vertical MOSFETs, the source, channel and drain can have atomically sharp interfaces, well controlled doping, and channel length controlled by the epitaxial process rather than by lithography and ion-implantation. With epitaxial growth, it is straightforward to do bandgap engineering by incorporating films such as Si1-xGex, and/or Si1-yCy and/or Si1-x-yGexCy, into any of the aforementioned regions. Suitable band offsets at the source/channel interface [2] can suppress DIBL, which is a key limitation to CMOS scaling. These advantages of Vertical MOSFETs are crucial for future CMOS technology nodes, such as 22nm and below.

SD-CMOS has a metallic drain region with work-function close to the mid-gap energy of the channel material, which can be a homogenous material, a random alloy, or a superlattice. The source region has a very narrow bandgap, achievable with (Si1-yCy)m-(Si1-xGex)n superlattices, whose mid-gap level is aligned with that of the channel region, and with band offsets with the channel region that are nearly symmetric for the conduction and valence bands. The source contact is a metal with a work-function close to the mid-gap level of the source and channel regions, which in turn are aligned with the work-function of the drain. The potential barrier, for electrons and holes from the source contact to the source region, is required to be just a few KT. For operation as NMOS and PMOS with nearly symmetric threshold voltages, the work-function of the gate electrode is also aligned with the mid-gap energy level of the channel.

SD-CMOS is unique due to its band alignments: symmetric band edges, from source to drain, with respect to the mid-gap energy (the “mirror” line). Such configuration can only be obtained in the absence of doping, which if present would immediately break that symmetry. The conduction and valence band edges are required to be asymmetric with respect to a cross-section line crossing the channel through the middle of the gate.

The conduction (valence) band offset between source and channel sets the barrier height for electrons (holes) in the OFF condition for NMOS (PMOS), while applying a voltage at the gate leads to the accumulation of electrons (holes) at the source/channel interface, thereby pushing the Fermi-Level in the source above (below) the conduction (valence) band edge of the channel for the ON condition. Band diagrams and a CMOS fabrication flow for SD-CMOS will be presented. [1] US Patent 6,674,099 [2] US Patent 5,914,504

High quality strained Ge (s-Ge) epitaxial layers are a promising candidate to achieve high mobility channel MOSFETs suitable for the 22 nm technology node and beyond, due to the intrinsically higher mobility of Ge compared to Si, and the additional performance enhancements from strain [1]. In order to achieve an s-Ge channel more than a few monolayers thick it is necessary to engineer a relaxed Si1-xGex buffer with a high Ge content (x > 0.5). We have recently reported high quality s-Ge layers grown by RP-CVD at low temperature (T ≤ 450 °C), on a fully relaxed Si0.2Ge0.8 buffer [2]. By using a reverse-grading approach, we achieved a high Ge composition in the buffer, with a smooth surface (rms surface roughness of ~2 nm), low threading dislocations density (~ 4 x 106 cm-2) and much thinner (~ 2.1 μm) than can be achieved with conventional linear grading [3].

In this work, the thermal stability of s-Ge epilayers (up to 80 nm thick) grown on relaxed Si0.2Ge0.8 buffers has been investigated by in-situ annealing in H2 ambient at temperatures up to 650 °C. These temperatures are similar to those currently used during fabrication of advanced CMOS devices. All s-Ge layers were grown at 400 °C using GeH4 gaseous precursor. The relaxation of the annealed layers has been studied using high-resolution XRD reciprocal space maps (RSMs), and was found to depend strongly on both annealing temperature and thickness of the Ge epilayer. Strained Ge layers up to 50 nm thick remained fully strained after annealing at 450 °C, whereas after annealing at 550 °C s-Ge layers thicker than 20 nm were on the onset of relaxation; after annealing at 650 °C all s-Ge layers showed significant relaxation with defects clearly visible at the Si0.2Ge0.8/Ge interface. All annealed s-Ge layers exhibited higher surface roughness than s-Ge control samples without annealing (rms ~ 2 nm). Annealing at 450 °C resulted in only a slight increase in surface roughness (rms ~ 3 nm), almost independent of s-Ge thickness. However, annealing at 550 °C and 650 °C resulted in significant surface roughening (with maximum rms values of 5 nm and 35 nm, respectively) due to the formation of Ge islands, which were observed by AFM. At these higher temperatures, the surface roughness of the s-Ge layers was found to be thickness dependent, with a Ge smoothing effect observed for layers greater than 50 nm.

These results are particularly important for the fabrication of s-Ge MOSFETs, for which the surface passivation prior to gate stack formation is critical to the performance of the device. Based on the results presented here, the thermal budget should be kept below 550 °C to avoid relaxation and roughening of the s-Ge epilayer, which could degrade the device performance.

Epitaxial GaAs layers had been grown by metal organic chemical vapor deposition at 620°C on Ge(100) susbtrates. The surface roughness of the GaAs is greater than that of GaAs bulk wafers and epilayer morphology is influenced by miscut of the Ge substrate. The GaAs/Ge interface is of good quality and devoid of misfit dislocations and antisite defects. However, Ge diffusion into GaAs occurred during epitaxy and resulted in auto-doping. ZrO2 was deposited by magnetron sputtering onto the epi-GaAs. Capacitance voltage measurements show that the TaN/ZrO2/epi-GaAs capacitor has an interfacical with more defects than a ZrO2/bulk GaAs interface. An improved interface with smaller frequency dispersion can be formed by atomic layer deposition of the high-k dielectric layer onto the epi-GaAs.

We have proposed spin quantum cross (SQC) devices, in which organic materials are sandwiched between two edges of magnetic thin films whose edges are crossed, towards the realization of novel beyond-CMOS switching devices. In SQC devices, nanometer-size junctions can be produced since the junction area is determined by the film thickness. In this study, we have fabricated Ni SQC devices with poly-3-hexylthiophene (P3HT): 6, 6-phenyl C61-butyric acid methyl ester (PCBM) organic materials and investigated the current-voltage (I-V) characteristics experimentally and theoretically. As a result of I-V measurements, ohmic I-V characteristics have been obtained at room temperature for Ni SQC devices with P3HT:PCBM organic materials, where the junction area is as small as 16 nm × 16 nm. This experimental result shows quantitative agreement with the theoretical calculation results performed within the framework of the Anderson model under the strong coupling limit. Our calculation also shows that a high on/off ratio beyond 10000:1 can be obtained in Ni SQC devices with P3HT:PCBM organic materials under the weak coupling condition.

A critical problem for the progression of CMOS electronics to the nanoscale is the reduction of power density, while at the same time preserving high speed performance. One of the most promising approaches is to aggressively reduce the power supply voltage by using a novel device, the tunneling MOSFET (TMOSFET), which is a MOSFET that operates by tunnel-injection of carriers from source to channel, rather than by conventional thermionic emission. TMOSFETs benefit from steep (sub-60mV/dec) gate turn-on characteristics. In this paper we show that TMOSFET designs based on staggered heterojunctions are particularly promising, since the choice of materials for the injector (source) and channel allows optimization of the tunneling probability at the heterojunction. Analysis and simulation of MOSFETs based on the GaAlSb / InGaAs material system are presented. The energy offset between the valence band of the injector and the conduction band of the channel at the heterojunction can be tailored over a wide range, from negative values (“offset” band lineup) to values in excess of 1eV. We find by simulation that for optimal values of effective heterojunction bandgap near 0.2eV, the resulting MOSFETs are capable of delivering >0.5mA/mm while maintaining on-off ratio greater than four orders of magnitude over voltage swing of 0.3V. We also discuss a variety of materials-related challenges that must be overcome to realize the predicted performance. Among these are the need to provide near ideal heterojunctions between the materials, employ high K dielectrics with very low interface state density, and achieve good alignment between the gate and the heterojunction. Different configurations for the tunneling MOSFETs are presented.