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The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements

Published online by Cambridge University Press:  23 April 2014

TOM CARROLL  and
JOAQUIM ORTEGA-CERDÀ
TOM CARROLL
Affiliation:
Department of Mathematics, University College Cork, Cork, Ireland email: t.carroll@ucc.ie
JOAQUIM ORTEGA-CERDÀ
Affiliation:
Departament de Matemàtica Aplicada i Anàlisi, Universitat de Barcelona, Gran Via 585, 08007 Barcelona, Spain email: jortega@ub.edu
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Abstract

A mathematical model of the voltage drop which arises in on-chip power distribution networks is used to compare the maximum voltage drop in the case of different geometric arrangements of the pads supplying power to the chip. These include the square or Manhattan power pad arrangement, which currently predominates, as well as equilateral triangular and hexagonal arrangements. In agreement with the findings in the literature and with physical and SPICE models, the equilateral triangular power pad arrangement is found to minimize the maximum voltage drop. This headline finding is a consequence of relatively simple formulas for the voltage drop, with explicit error bounds, which are established using complex analysis techniques, and elliptic functions in particular.

Keywords

Mathematical problems of computer architectureElliptic functions and integralsPoisson's equation
Type
Papers
Information
European Journal of Applied Mathematics , Volume 25 , Issue 5 , October 2014 , pp. 531 - 551
Copyright
Copyright © Cambridge University Press 2014 

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