Journal of Functional Programming
- Journal of Functional Programming / Volume 22 / Special Issue 4-5 / September 2012, pp 574-613
- Copyright © Cambridge University Press 2012
- DOI: http://dx.doi.org/10.1017/S0956796812000214 (About DOI), Published online: 10 July 2012
Articles
The Reduceron reconfigured and re-evaluated
MATTHEW NAYLORa1 and COLIN RUNCIMANa1
a1 Department of Computer Science, University of York, York, North Yorkshire, UK (e-mail: mfn@cs.york.ac.uk, colin@cs.york.ac.uk)
Abstract
A new version of a special-purpose processor for running lazy functional programs is presented. This processor – the Reduceron – exploits parallel memories and dynamic analyses to increase evaluation speed, and is implemented using reconfigurable hardware. Compared to a more conventional functional language implementation targeting a standard RISC processor running on the same reconfigurable hardware, the Reduceron offers a significant improvement in run-time performance.
(Online publication July 10 2012)
