MRS Proceedings


Reconfigurable Graphene Logic Device Based on Tilted P-N Junctions

2010 MRS Fall Meeting.

Sansiri Tanachutiwata1, Ji Ung Leea1 and Wei Wanga1

a1 College of Nanoscale Science and Engineering, University at Albany 257 Fuller Rd., Albany, NY 12203 USA


In this paper, we introduce a novel reconfigurable graphene logic based on graphene p-n junctions. In this logic device, switching is accomplished by using co-planar split gates that modulate the properties that are unique to graphene, including ambipolar conduction, electrostatic doping, and angular dependent carrier reflection. In addition, the use of these control gates can dynamically change the operation of the device, leading to reconfigurable multi-functional logic. A device model is derived from carrier transmission probability across the p-n junction for allowing quantitative comparison to CMOS logic. Based on this model, we show that the proposed graphene logic has significant advantages over CMOS gate in terms of area, delay, power, and signal restoration. Furthermore, the device utilizes a large graphene sheet with minimal patterning, allowing feasible integration with CMOS circuits, for potential CMOS-graphene hybrid circuits.

(Online publication June 01 2011)

Key Words:

  • devices;
  • electrical properties;
  • electronic structure