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Influence of Embedded a-Si:H Layer Location on Floating-gate a-Si:H TFT Memory Functions

Published online by Cambridge University Press:  01 February 2011

Yue Kuo  and
Mary Coan
Yue Kuo
Affiliation:
yuekuo@tamu.edu, Texas A&M University, Thin Film Nano & Microelectronics Research Laboratory, College Station, Texas, United States
Mary Coan
Affiliation:
yuekuo@neo.tamu.edu, Texas A&M University, Thin Film Nano & Microelectronics Research Laboratory, College Station, Texas, United States
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Abstract

The influence of the location of the embedded a-Si:H layer in the gate dielectric film of the floating-gate a-Si:H TFT on the charge trapping and detrapping mechanisms has been investigated. The thin channel-contact SiNx gate dielectric layer favors both hole and electron trappings under the proper gate voltage condition. The sweep gate voltage affect the locations and shapes of forward and backward transfer characteristics curves, which determines the memory function. In order to achieve a large memory window, both the location of the embedded a-Si:H layer and the gate voltage sweep range need to be optimized.

Keywords

electronic structurethin filmmemory
Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 1245: Symposium A – Amorphous and Polycrystalline Thin-Film Silicon Science and Technology-2010 , 2010 , 1245-A12-01
Copyright
Copyright © Materials Research Society 2010

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References

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